1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, a sense amplifier drive circuit of a semiconductor memory device and a method for amplifying data.
2. Background of the Related Art
A basic DRAM (Dynamic Random Access Memory) cell structure includes a single transistor and a single capacitor connected to each other. In the DRAM cell, a word line is activated during reading, writing and refreshing operations, and a charge that is stored in the single capacitor of the DRAM cell is carried on a bit line and amplified by a sense amplifier. In this respect, the bit line is precharged before the word line is activated.
When the charge carried on the bit line is amplified by the sense amplifier, the sense amplifier is first overdriven with a pre-set overdrive voltage and is then driven by an internal power supply voltage, for a speedy and easy amplification of the charge.
FIG. 1 illustrates a schematic circuit diagram of a sense amplifier circuit of a related art, and includes a sense amplifier 10 that amplifies a data signal carried on a bit line BL and a bit line bar BLB. A sense amplifier drive unit 20 selectively applies an overdrive voltage or an internal power supply voltage to the sense amplifier 10. A control signal generator 30 generates first and second PMOS control signals SAP1 and SAP2, and an NMOS control signal SAN, to control the sense amplifier drive unit 20.
The sense amplifier 10 is a related art latch-type sense amplifier including a first PMOS transistor PM1 and a first NMOS transistor NM1, connected in series between a PMOS drive line CSP and an NMOS drive line CSN, with their respective gates being commonly connected to a bit line BL via a first node N1. A second PMOS transistor PM2 and a second NMOS transistor NM2 are connected in series between the PMOS drive line CSP and the NMOS drive line CSN, with their respective gates being commonly connected to the bit line bar BLB via a second node N2. Here, the commonly connected drains of the second PMOS transistor PM2 and the second NMOS transistor NM2 serve as the first node N1, while the commonly connected drains of the first PMOS transistor PM1 and the first NMOS transistor NM1 serve as the second node N2.
The sense amplifier drive unit 20 includes a third NMOS transistor NM3 that receives the first control signal SAP1 at its gate and selectively applies an overdrive voltage VDDCLP to the PMOS drive line CSP of the sense amplifier 10. A fourth NMOS transistor NM4 receives the second PMOS control signal SAP2 at its gate and selectively applies an internal power supply voltage VDL to the PMOS drive line CSP of the sense amplifier 10. In addition, a fifth NMOS transistor NM5 receives the NMOS control signal SAN at its gate and selectively connecting the NMOS drive line CSN of sense amplifier 10 to a ground voltage VSS.
FIG. 2 illustrates a detailed schematic circuit diagram of the control signal generator 30 that generates the first and second PMOS control signals SAP1 and SAP2, and the NMOS control signal SAN. As shown in FIG. 2, the control signal generator 30 includes first and second inverters INV1 and INV2, each inverting a sense amplifier enable bar signal SAENB. A delay circuit DE1 delays an output signal from the second inverter INV2 for a predetermined time. A third inverter INV3 inverts an output signal from the delay circuit DE1. A first NOR gate NOR1 provides a NOR operation to an output signal from the third inverter INV3 and the sense amplifier enable bar signal SAENB. A fourth inverter INV4 inverts an output signal from the first inverter INV1, and outputs the Inverted output signal to a logic circuit 31. A fifth inverter INV5 inverts an output signal from the first NOR gate NOR1 and outputs the inverted output signal to the logic circuit 31.
The logic circuit 31 includes three control signal generator sections 31a-c, and a sixth inverter INV6 that inverts the output signal from the fifth inverter INV5. The first control signal generator section 31a includes a second NOR gate NOR2 that provides a not OR operation to the output signal from the sixth inverter INV6 and an output signal from the fourth inverter INV4. Seventh and eighth inverters INV7 and INV8 sequentially invert an output signal from the second NOR gate NOR2 as the first PMOS control signal SAP1.
The second control signal generator section 31b includes a ninth inverter INV9 that inverts an output signal from the sixth inverter INV6, and a first NAND gate ND1 that provides a not AND operation to the output signal from the fourth inverter INV4 and an output signal of the ninth inverter INV9. Tenth and eleventh inverters INV10 and INV11 sequentially invert an output signal from the first NAND gate ND1 as the NMOS control signal SAN. The third control signal generator section 31c includes twelfth to fifteenth inverters INV12-INV15 that sequentially invert the output signal from the sixth inverter INV6 as the second PMOS control signal SAP2.
FIG. 3 illustrates an operational timing diagram of the related art sense amplifier drive unit of FIG. 1. When the sense amplifier enable bar signal SAENB is applied to the control signal generator 30, the first and second PMOS control signals SAP1 and SAP2 and the NMOS control signal SAN are output to the sense amplifier drive unit 20.
As shown in FIG. 3, the first and the second PMOS control signals SAP1 and SAP2 are sequentially enabled. That is, at the time when the first PMOS control signal SAP1 is disabled after being enabled, the second PMOS control signal SAP2 is enabled. Accordingly, the third and fourth NMOS transistors NM3 and NM4 of the sense amplifier drive unit 20 are sequentially turned on and the overdrive voltage VDDCLP and the internal power supply voltage VDL are sequentially applied to the PMOS drive line CSP of the sense amplifier 10.
In other words, while the first PMOS control signal SAP1 is enabled, the third NMOS transistor NM3 is turned on, and the sense amplifier 10 is driven by the overdrive voltage VDDCLP, so that the data carried on the bit line BL and the bit line bar BLB is amplified to the level of the overdrive voltage VDDCLP.
Subsequently, the first PMOS control signal SAP1 is disabled to turn off the third NMOS transistor NM3, and at this time, the second PMOS control signal SAP2 is enabled to turn on the fourth NMOS transistor NM4. Then, the sense amplifier 10 is driven by the internal power supply voltage VDL, so that the data carried on the bit line BL and the bit line bar BLB is amplified to the level of the internal power supply voltage VDL.
The related sense amplifier drive circuit, however, has a problem that an unnecessary current consumption unavoidably occurs because the overdrive voltage is supplied to the sense amplifier 10 during a refreshing operation.
An object of the present invention is to substantially obviate one or more of the problems of the related art and provide at least the advantages set forth below.
Another object of the present invention is to reduce an unnecessary current consumption.
Another object of the present invention is to prevent an application of an overdrive voltage during a refresh operation.
The objects of the present invention can be achieved, in whole or in parts, by a sense amplifier drive circuit including a sense amplifier that amplifies data carried on a bit line and a bit line bar; a sense amplifier drive unit that selectively applies an overdrive voltage and an internal power supply voltage to the sense amplifier; and a control signal generator that combines a sense amplifier enable bar signal and a refresh enable signal, and generates control signals to control the sense amplifier drive unit.
The objects of the present invention can also be achieved, in whole or in parts, by a circuit including a control signal generator that receives a sense amplifier signal and a refresh signal, that generates a first set of control signals, based on the sense amplifier signal, when the refresh signal is at a first level, and that generates a second set of control signals, based on the sense amplifier signal, when the refresh signal is at a second level. The circuit also includes a first drive circuit coupled to the control signal generator, that enable the application of a first voltage according the first and second set of control signals, and a second drive circuit, coupled to the control signal generator, that enables the application of a second voltage according to the first set of control signals and disables the application of the second voltage according to the second set of control signals.
The objects of the present invention can further be achieved, in a whole or in parts, by a method for amplifying data, including receiving a sense amplifier signal and a refresh signal, generating a first set of control signals, based on the sense amplifier signal, when the refresh signal is at a first level, generating a second set of control signals, based on the sense amplifier signal, when the refresh signal is at a second level, enabling an application of a first voltage to the data according to the first and second set of control signals, enabling an application of a second voltage to the data according to the first set of control signals, and disabling an application of a second voltage according to the second set of control signals.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.